The present disclosure relates to bidirectional switch circuits and switch devices.
In a switch circuit mounted in a mobile communication device such as a cellular phone, field-effect transistors (FETs) are used, for example. For use in the switch circuit constituted of FETs, such a configuration is well-known that a plurality of FETs are connected in multiple stages (multistage-connected) to improve withstand voltage of the switch circuit in order to handle a relatively high input voltage. In the above configuration, because a voltage divided by the number of stages of the multistage-connected FETs is applied across a source and a drain of each FET, a permissible input voltage can be set in accordance with the number of stages of the FETs.
In this case, since each FET has parasitic capacitance, the voltage of a signal supplied to an input terminal is not equally divided due to the influence of the parasitic capacitance. Because of this, such a phenomenon is generated that a voltage applied across the source and drain of each FET becomes gradually larger from an output terminal side toward the input terminal side. In this case, a voltage exceeding the withstand voltage is applied across the source and drain of each of the FETs relatively close to the input terminal, which raises a risk of breakdown of the FETs. As such, it is preferable to resolve the un-uniformity of the voltage applied across the source and drain of each of the FETs in order to prevent the breakdown of the FETs due to the increase in input voltage in the switch circuit.
For example, U.S. Pat. No. 9,106,227 discloses a configuration in which voltage is equally supplied across the source and drain of each FET by additionally providing capacitance elements connected in parallel over some FETs that are continuously connected from the FET closest to one terminal. In this configuration, the source of the FET closest to the one terminal (that is, the terminal where the amplitude of a voltage derived from an input signal is relatively large) and the drain of each of the FETs are directly connected to each other so as to raise the drain voltage of each FET, thereby solving the un-uniformity of the voltage across the source and drain. Moreover, in the stated configuration, capacitance elements are additionally provided in parallel over some FETs that are continuously connected from the other terminal in a similar manner. This makes it possible to resolve the un-uniformity of the voltage across the source and drain of each of the FETs regardless of whether the signal is supplied from the one terminal or from the other terminal.
According to the configuration disclosed in U.S. Pat. No. 9,106,227, because the additionally provided capacitance elements are connected from the FET closest to the one terminal or from the FET closest to the other terminal, capacitance values of each of the capacitance elements can become relatively large, thereby raising a problem that characteristics of insertion loss, isolation, or the like are degraded when the switch circuit is turned off.